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Design Rules

Design Rules schematic

 

Spacing - Clearance :

 

 Class 5

 

Min. SpacingOuter LayerInner Layer
Track-Track (A) 150 µm 150 µm
Track-Pad (B) 150 µm 150 µm
Pad-Pad (C) 170 µm 150 µm

 

 Class 6

 

Min. SpacingOuter LayerInner Layer
Track-Track (A) 120 µm 120 µm
Track-Pad (B) 120 µm 120 µm
Pad-Pad (C) 150 µm 120 µm


Track Width (D) :

 

 

 Class 5

 

Outer LayerInner Layer
150 µm 150 µm

 

 Class 6

 

Outer LayerInner Layer
120 µm 120 µm


Plated Through Hole Vias :

 

 Class 5

 

Pad Size (E)Drill Hole (F)Final Hole Diameter (G)ToleranceInner Layer Copper Clearance (H)Solder Mask Opening (I)
0.6 mm 0.35 mm 0.25 mm +0.10 / -0.05 mm ≥ 0.85 mm ≥ 0.40 mm

 

 Class 6

 

Pad Size (E)Drill Hole (F)Final Hole Diameter (G)ToleranceInner Layer Copper Clearance (H)Solder Mask Opening (I)
0.55 mm 0.30 mm 0.20 mm +0.10 / -0.05 mm ≥ 0.8 mm ≥ 0.40 mm


Solder Mask :

 

Clearance (J)Coverage (K)Solder Mask Web (L)Via Opening (I)
≥ 100 µm ≥ 50 µm ≥ 125 µm ≥ 0.40 mm


Silk Screen :

 

Line Width (M)Font Height (N)Distance to Solder Mask Opening (O)
≥ 100 µm 1.50 mm ≥ 100 µm


Other Design Parameters :

 

Spacing - Clearanceroutingscoring
Copper to Board Edge ≥ 0.25 mm (P) ≥ 0.30 mm (P)
Copper to Non Plated Through Hole ≥ 0.25 mm


ParametersValue
Hole to Hole Spacing (NPTH, Border to Border) ≥ 0.10 mm
Board to Board Spacing (in Panel) ≥ 1.6 mm